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1 ? fn9027.7 ISL6558 multi-purpose precision multi-phase pwm controller with op tional active voltage positioning the ISL6558 is a multi-phase pwm controller, which in combination with the hip6601b, hip6602b, hip6603b, or isl6605 companion gate drivers form a complete solution for high-current, high slew-rate applications. the ISL6558 regulates output voltage, balanc es load currents and provides protective functions for two to four synchronous rectified buck converter channels. a novel approach to current sensing is used to reduce overall solution cost and improve efficiency. the voltage developed across the lower mosfet during conduction is sampled and fed back to the controller. this lossless current-sensing approach enables the controller to maintain phase-current balance between the power channels, provide overcurrent protection, and permit droop compensation. optional output voltage ?droop? or active voltage positioning is supported via the droop pin. ta king advantage of this feature reduces the size and cost of th e output capacitors required to support a load transient. in the event of an overvoltage, the controller monitors and responds to reduce the risk of damage to load devices. undervoltage conditions are indicated through a pgood transition. overcurrent conditions cause the converter to shutdown limiting the exposure of load devices. these integrated monitoring and protection features provide a safe environment for microprocessors and other advanced low voltage circuits. features pb-free available as an option multi-phase power conversion - 2-, 3-, or 4-phase operation optional output voltage droop precision channel-current balance lossless current sensing precision reference voltage -0.8v 1.5 % over -40 c - 85 c range -0.8v 1.0 % over 0 c - 70 c range fast transient response overcurrent and overvoltage protection digital soft-start power good indication high ripple frequency (80khz to 1.5mhz) qfn package - compliant to jedec pub95 mo-220 qfn-quad flat no leads-product outline - near chip-scale package footprint; improves pcb efficiency and thinner in profile applications power supply control for microprocessors low output voltage, high current dc-dc converters voltage regulator modules servers and workstations memory and accelerated graphics port supplies communication processor and personal computer peripherals pinouts ordering information part number temp. ( c) package pkg. dwg. # ISL6558cb* 0 to 70 16 ld soic m16.15 ISL6558cbza* (see note) 0 to 70 16 ld soic (pb-free) m16.15 ISL6558cr* 0 to 70 20 ld 5x5 qfn l20.5x5 ISL6558ib* -40 to 85 16 ld soic m16.15 ISL6558ir* -40 to 85 20 ld 5x5 qfn l20.5x5 ISL6558eval1 evaluation platform 1 (soic package, ISL6558cb + hip6601bcb) ISL6558eval2 evaluation platform 2 (qfn package, ISL6558cr + isl6605cr) note: intersil pb-free products em ploy special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow te mperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020b. *add "-t" suffix for tape and reel. comp droop fb vsen gnd pwm3 pgood pwm4 isen4 pwm2 isen1 pwm1 vcc isen2 gnd n/c n/c isen3 vcc 1 2 3 4 5 678910 15 14 13 12 11 20 19 18 17 16 fs/en 9 10 11 12 13 14 16 15 8 7 6 5 4 3 2 1 v cc pgood comp droop fb vsen gnd fs/en pwm4 isen1 pwm1 pwm2 isen4 isen2 isen3 pwm3 ISL6558 (16 lead soic) top view ISL6558 (20 lead 5x5 qfn) top view data sheet may, 2004 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2001-2004. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 block diagram 0.8v current correction ov latch power-on reset (por) soft - start and fault logic channel detector - + uv + - e/a + - pwm pwm oc + - pwm1 pwm2 pwm3 pwm4 gnd pgood fb fs/en s three-state i total + - + - + - + - + + + + + - phase + - pwm + - pwm clock and number droop comp vsen generator sawtooth x1.15 x 0.9 isen1 isen2 isen3 isen4 + - ov reference i trip r v cc ISL6558
3 functional pin description note: pin numbers refer to the soic package. check pinout diagrams for qfn pin numbers. vcc (pin 1) supplies all the power necessary to operate the chip. the ic starts to operate when the voltage on this pin exceeds the rising por threshold and shuts down when the voltage on this pin drops below the falling por threshold. connect this pin to a 5v (5%) supply. pgood (pin 2) power good is an open drain output used to indicate the status of the output voltage. this pin is pulled low when the converter output voltage is either 10% below or 15% above the reference voltage. comp (pin 3) output of the internal error amplifier. connect this pin to the external feedback compensation network. droop (pin 4) output voltage droop or active voltage positioning is provided by connecting this pin to the fb pin. an internal current source creates the droop across an external feedback resistor, r fb . if no droop is desired, this pin must be left open. fb (pin 5) the fb pin is the inverting input of the internal error amplifier. connect this pin to the external feedback compensation network and a resistor divider from the output for proper control and protection of converter load. vsen (pin 6) this pin is connected through a resistor divider to the converter?s output voltage to provide remote sensing. the undervoltage and overvoltage pr otection comparators trigger off this input. fs/en (pin 7) connecting a resistor from this pin to ground sets the internal oscillator frequency. the switching frequency, f sw , of the converter is adjustable between 80khz and 1.5mhz. pulling this pin to ground disables the converter and three- states the pwm outputs. gnd (pin 8) bias and reference ground for all controller signals. pwm1 (pin 13), pwm2 (pin 12), pwm3 (pin 9), pwm4 (pin 16) the controller pwm drive signals are connected to the individual hip660x driver pwm input pins. the number of active channels is determined by the state of pwm3 and pwm4. if pwm3 is tied to vcc, this indicates to the controller that two channel operation is desired. in this case, pwm4 should be left open or tied to vcc. tying pwm4 to vcc indicates that three channel operation is desired. isen1 (pin 14), isen2 (pin 11), isen3 (pin 10), isen4 (pin 15) these pins are used to monitor the voltage drop across the lower mosfets for current feedback, output voltage droop and overcurrent protection. a resistor must be placed in series with each of these inputs and their respective phase node. the resistor is sized such that the current feedback is 50 a at full load. sense lines corresponding to inactive channels should be left open. inactive channels are those in which the pwm pin has been tied to vcc or left open. thermal pad (in qfn only) in the qfn package, the pad underneath the center of the ic is a thermal substrate. the pcb ?thermal land? design for this exposed die pad should include thermal vias that drop down and connect to one or more buried copper plane(s). this combination of vias for vertical heat escape and buried planes for heat spreading allows the qfn to achieve its full thermal potential. this pad should be either grounded or floating, and it should not be connected to other nodes. refer to tb389 for design guidelines. ISL6558
4 typical application - 3 phase converter pwm control ISL6558 pgood fb +5v comp pwm3 pwm2 pwm1 isen3 isen2 isen1 vsen pwm vcc +5v boot ugate phase lgate +12v v out driver hip6601b pwm vcc +5v boot ugate phase lgate +12v pvcc pwm vcc +5v boot ugate phase lgate +12v driver hip6601b pvcc driver hip6601b pvcc fs/en pwm4 isen4 nc gnd gnd gnd gnd v cc droop r os r fb r os v out = 0.8v(r fb + r os )/r os r fb r c c c r isen1 r isen2 r isen3 r t ISL6558
5 absolute maximum ratings supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7v input, output, or i/o voltage . . . . . . . . . . . gnd -0.3v to v cc +0.3v esd classification human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250v recommended operating conditions supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 5% ambient temperature. . . . . . . . . . . . . . . . . . . . . . . . . .-40c to 85c maximum operating junction temperature . . . . . . . . . . . . . . . 125c thermal information thermal resistance (typical notes 1, 2, 3) ja (c/w) jc (c/w) soic package (note 1) . . . . . . . . . . . . 70 n/a qfn package (notes 2, 3) . . . . . . . . . . 35 5 maximum junction temperature. . . . . . . . . . . . . . . . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . 300c (soic - lead tips only) caution: stress above those listed in ?absol ute maximum ratings? may cause permanent dam age to the device. this is a stress onl y rating and operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. notes: 1. ja is measured with the component mounted on a high effective ther mal conductivity test board in fr ee air. see tech brief tb379 f or details. 2. ja is measured in free air with the component mounted on a high effe ctive thermal conductivity test board with ?direct attach? fe atures. see tech brief tb379 for details. 3. jc , "case temperature" location is at the center of the exposed metal pad on the package underside. electrical specifications operating conditions: v cc = 5v, t a = -40c to 85c. unless otherwise specified. parameter test conditions min typ max units input supply power input supply current vcc = 5vdc; r t = 100k ? 1% - 10 15 ma power-on reset (por) vcc rising threshold 4.25 4.38 4.5 v vcc falling threshold 3.75 3.88 4.00 v reference voltage reference voltage ISL6558cb, ISL6558cr, t a = 0c to 70c 0.792 0.8 0.808 v ISL6558ib, ISL6558ir, t a = -40c to 85c 0.788 0.8 0.812 v system accuracy ISL6558cb, ISL6558cr, t a = 0c to 70c -1.0 - 1.0 % ISL6558ib, ISL6558ir, t a = -40c to 85c -1.5 - 1.5 % oscillator channel frequency accuracy r t = 100k ?. 1% 224 280 336 khz adjustment range see figure 3 0.08 - 1.5 mhz disable voltage maximum voltage at fs/en to disable controller. i fs/en = 1ma - 1.2 1.0 v sawtooth amplitude -1.33-v p-p channel maximum duty cycle, by design -75- % error amplifier dc gain r l = 10k to ground - 72 - db gain-bandwidth product c l = 100pf, r l = 10k to ground - 18 - mhz slew rate c l = 100pf, load = 400 a-5.3-v/ s maximum output voltage r l = 10k to ground 3.6 4.1 - v isen recommended full scale input current -50- a overcurrent trip level 67 - 85 a ISL6558
6 power good monitor undervoltage threshold vsen rising - 0.92 - v ref undervoltage threshold vsen falling - 0.90 - v ref pgood low output voltage i pgood = 4ma - 0.18 0.4 v protection overvoltage threshold vsen ri sing, ISL6558cb, ISL6558cr, t a = 0c to 70c 1.12 1.15 1.2 v ref vsen rising, ISL6558ib, ISL6558ir, t a = -40c to 85c 1.085 1.15 1.2 v ref percent overvoltage hysteresis vsen falling after overvoltage - 2 - % electrical specifications operating conditions: v cc = 5v, t a = -40c to 85c. unless otherwise specified. (continued) parameter test conditions min typ max units current sensing + r isen1 + correction error amplifier fb isen1 r fb v out q3 q4 l 02 phase pwm1 i l2 0.8v c out r load v in hip6601b - q1 q2 l 01 phase i l1 v in hip6601b current sensing correction pwm2 - i total + + + - r isen2 isen2 - - current averaging figure 1. simplified block diagram of the ISL6558 vo ltage and current control loops configured for a two channel converter droop r os pwm circuit pwm circuit v error1 v error2 i droop ISL6558
7 operation figure 1 shows a simplified diagram of the voltage regulation and current control loops for a two-phase converter. both voltage and current feedback are used to precisely regulate output voltage and tightly c ontrol phase currents, i l1 and i l2 , of the two power channels. voltage loop output voltage feedback is applied via the resistor combination of r fb and r os to the inverting input of the error amplifier. this signal drives the error amplifier output high or low, depending upon the scaled output voltage in relation to the reference voltage of 0.8v. the amplifier output voltage is distributed among the active pwm channels and summed with their individual current correction signals. the resultant signal, v error , is fed into the pwm control circuitry for each channel. within this block, the signal is compared with a sawtooth ramp signal. the sawtooth ramp signal applied to each channel is out-of-phase with the others. the resulting duty cycle signal for each channel is determined by the movement of the correction voltage, v error , relative to the sawtooth ramp. the individual duty cycle signals are sent to their respective hip660x gate drivers from the pwm pins. the hip660x gate drivers then switch their upper and lower mosfets in accordance to this pwm signal. current loop the current control loop keeps the channel currents in balance. during the pwm off-time of each channel, the voltage developed across the r ds(on) of the lower mosfet is sampled. the current is scaled by the r isen resistor and provides feedback proportional to the output current of each channel. the scaled output current from all active channels are combined to create an average current reference, i total , relative to the converter? s total output current. this signal is then subtracted from the individual channel scaled output currents to produce a current correction signal for each channel. the current correction signal keeps each channel?s output current contribution balanced relative to the other active channels. each current correction signal is then subtracted from the error am plifier output and fed to the individual channel pwm circuits. for example, assume the voltage sampled across q4 in figure 1 is higher than that sampled across q2. the isen2 current would be higher then isen1. when the two reference currents are averaged, they still accurately represent the total output curr ent of the converter. the reference current i total is then subtracted from the isen currents. this results in a positive offset for channel 2 and a negative offset for channel 1. these offsets are subtracted from the error amplifier signal and perform phase balance correction. the v error2 signal is reduced, while v error1 would be increased. the pwm circuit would then reduce the pulse width to lower the output current contribution by channel 2, while doing the opposite to channel 1. droop compensation microprocessors and other peripherals tend to change their load current demands often from near no-load to full load during operation. these same devices require minimal output voltage deviation from nominal during a load step. a high di/dt load step will cause an output voltage spike. the amplitude of the spike is dict ated by the output capacitor esr (effective series resistance) multiplied by the load step magnitude and output capacitor esl (equivalent series inductance) times the load step di/dt. a positive load step produces a negative output voltage spike and visa versa. the overall output voltage deviation could exceed the tolerance of some devices. one widely accepted solution to this problem is output voltage ?droop? or active voltage positioning. droop is set relative to the output voltage tolerance specifications of the load device. most device tolerance specifications straddle the nominal output voltage. at no- load, the output voltage is se t to a slightly higher than nominal level, v out,nl . at full load, the output voltage is set to a slightly lower than nominal level, v out,fl . the result is a desire to have an output voltage characteristic as shown by the load line in figure 2. with droop implemented and a positive load step, the resulting negative output voltage spike begins from the slightly elevated level of v out,nl . similarly, if the load steps from full load, i out,max , back to no-load, i out,nl , the output voltage starts from the slightly lower v out,fl position. these few millivolts of offset help reduce the size and cost of output capacitors required to handle a given load step. droop is an optional feature of the ISL6558. it is implemented by connecting the droop and fb pins as shown in figure 1. an internal current source, i droop , feeds out of the droop pin. the magnitude of i droop is controlled by the scaled repr esentation of t he total output current created from the individual isen currents. i droop creates a voltage drop across r fb and offsets the output v out,nl v out,fl i out,max i out,nl figure 2. simple output device load line v out,nom i out,mid nominal load line droop load lin e ISL6558
8 voltage feedback seen at the fb pin, effectively creating the output voltage droop desired as a function of load current. selecting r fb and r os if output droop compensation is not required the droop pin must be left open. simply select a value for r fb and calculate r os based on the following equation: in applications where droop compensation is desired, tie the droop and fb pins together. select r fb first given the following equation, where v droop is the desired amount of output voltage droop at full load. this equation is contingent upon the correct selection of th e isen resistors discussed in the fault protection section. calculate r os based on r fb using the following equation. where v out,nl is the desired output voltage under no-load conditions. initialization many functions are initiated by a rising supply voltage applied to the vcc pin of th e ISL6558. until the supply voltage reaches the power-on reset (por) vcc rising threshold, the pwm drive signals are held in three-state. this results in no gate drive generation by the hip660x gate drivers to the output mosfets. once the supply voltage exceeds the por rising threshold, the soft-start interval is initiated. if the supply voltage drops below the por falling threshold, por shutdown is triggered and the pwm outputs are again driven to three-state. the fs/en pin can also be used to initialize the converter. holding this pin to ground over rides the onset of soft-start. once this pin is released, soft-start is initialized and the converter output will begin to ramp. if fs/en is grounded during operation, a por shutdown is triggered and the pwm outputs are three-stated. toggling this pin after an overvoltage event will not reset the controller; v cc must be cycled. sequencing of the input supplies is recommended. an overcurrent spike due to supply voltage sequencing could occur if the controller becomes active before the drivers. if the por rising threshold of the controller is met before that of the drivers, then a soft-star t interval is started and could be completed before the drivers are active. once the drivers become active the controller will be demanding maximum duty cycle due to the lack of output voltage and could cause an overcurrent trip. a soft-start interval would be initiated shortly after this event and normal pwm operation would result. the supply voltages should be sequenced such that the controller and gate drivers are initialized simultaneously or the drivers become active just before the controller. most atx supplies control the rise times of the individual voltage outputs and insure proper sequencing. soft-start interval before a soft-start cycle is init iated, the controller holds the active channel pwm drive signals in three-state as long as the fs/en pin is held at groun d or the voltage applied to vcc remains below the por rising threshold. once vcc rises above the por rising threshold and the fs/en pin is released from ground, a soft-start interval is initiated. pwm operation begins and the resulting slow ramp- up of output voltage avoids hitting an overcurrent trip by slowly charging the discharged output capacitors. the soft- start interval ends when the pgood signal transitions to indicate the output voltage is within specification. the soft-start interval is digitally controlled by the selection of switching frequency. the maximum soft-start interval, ss interval , can be estimated for a given application: where f sw is the channel switching frequency. the converter used to create the waveforms in figure 3 has a switching frequency of 125khz. the soft-start interval calculated for this converter is just over 16ms. from the waveforms, the actual soft-start interval is just under 16ms. pwm drive signals the ISL6558 provides pwm channel drive signals for control of 2-, 3-, or 4-phase converters. the pwm signals drive the associated hip660x gate drivers for each power channel. the number of active channels is determined by the status of pwm3 and pwm4. if pwm3 is tied to vcc, then the controller will interpret this as two channel operation and only pwm1 and pwm2 will be active. since pwm4 is not active under these conditions, simply tie it to vcc or leave it open. if only pwm4 is tied to vcc, then the remaining three channels are all considered ac tive by the controller. r os r fb x 0.8v v out 0.8v ? ---------------------------------- = (eq. 1) r fb v droop 50 a ------------------------ -20 3 10 xv droop == (eq. 2) r os r fb x 0.8v v out nl , 0.8v ? -------------------------------------------- = (eq. 3) ss interval 2048 f sw ------------ - = (eq. 4) 0v vcc, 2v/div v out , 0.5v/div 0v pgood, 2v/div 0v 0v fb, 0.5v/div 2ms/div por rising threshold figure 3. soft-start waveforms ISL6558
9 the pwm drive signals are switched out of phase. the pwm drive signal phase relationship is 360 divided by the number of active channels. figure shows the pwm drive signals for a four channel converter running at 125khz. each pwm drive signal is 90 out of phase with the other. frequency setting a resistor, r t , connected between the fs/en pin and ground sets the frequency of the internal oscillator. tying the fs/en pin to ground disables the oscillator, thus shutting down the converter. the resistor can be calculated given the desired channel switching frequency, f sw . figure 5 provides a graph of oscillator frequency vs r t . the maximum recommended channel frequency is 1.5mhz. reference voltage an internal 0.8v reference is used for both pwm duty cycle determination as well as out put voltage protection. the reference is trimmed such that the system, including amplifier offset voltages, is accurate to 1 % over temperature range. fault protection the ISL6558 protects the load device from damaging stress levels. the overcurrent trip point is integral in preventing output shorts of varying degrees from causing current spikes which would damage a load device. the output voltage detection features insure a safe window of operation for the load device. overcurrent the r isen resistor scales the voltage sampled across the lower mosfet and provides current feedback proportional to the output current of each active channel. the isen currents from all the active channels are averaged together to form a scaled version of the total output current, i total . 0v pwm1, 5v/div figure 4. four active channel pwm drive signals 1ms/div 0v pwm3, 5v/div pwm4, 5v/div 0v 0v pwm2, 5v/div r t 10 10.9 1.1 f sw log ? = (eq. 5) 50 100 10 20 200 500 1,000 2,000 1 2 5 10 20 50 100 200 500 1,000 r t - kw channel oscillator frequency, f sw , [khz] figure 5. oscillator frequency vs r t oc + - i total + isen1 i trip 82.5 a figure 6. internal overcurrent detection circuitry n n = active channels isen4 ISL6558 isen3 isen2 + + + 0v 0a 0v figure 7. overcurrent operation 10ms/div i out (5a/div) v out (1v/div) short applied short removed pgood (5v/div) ISL6558
10 see figure 6. i total is compared with an internally generated overcurrent trip current, i trip . the overcurrent trip current source is trimmed to 82.5 a. if i total exceeds the i trip level, then the controller forces all pwm outputs into three-state. this condition results in the hip660x gate drivers removing drive to the mosfets. the vsen voltage will begin to fall and once it descends below the pgood falling threshold, the pgood signal transitions low. a delay time, equal to the soft-start interval, is entered to allow the disturbance to clear. after the delay time, the controller then initiates a second soft-start interval. if the output voltage comes up and regulation is achieved, pgood transitions high. if the oc trip current is exceeded during the soft start interval, the controller will again shut down pwm operation and three-state the drivers. the pgood signal will remain low and the soft-start interval will be allowed to expire. another soft-start interval will be initiated after the delay interval. if an overcurrent trip occurs again, this same cycle repeats un til the fault is removed. the oc function is shown in figure 7 for a hard short of the output which is applied for only a brief moment. the converter quickly detects the short and attempts to restart twice before the short is removed. overcurrent protection reduce s the regulator rms output current under worst case conditions to 95% of the full load current. selecting r isen the procedure for determining the value of r isen is to insure that it scales a channel?s maximum output current to 50 a. this will insure that the overcurrent trip point is properly detected when a cu rrent limit of 165% of the converter?s full load current is breached. the isen resistor can be calculated as follows: where i fl is the maximum output current demanded by the load device and ?n? is the number of active channels. oc trip level adjustment setting the full load reference current, i total , to 50 a is recommended for most applications. the ratio between the desired full load reference current and the internally set overcurrent trip current is the overcurrent trip ratio, k oc . for those applications where an oc trip level of 1.65 times i total is insufficient, the full load reference current can be scaled differently. care must be taken in selection of certain components once the desired oc trip ratio is determined. the new overcurrent trip ratio is then used to calculate the isen resistors for the new full load reference current. one commonly over looked component which will change due to the new overcurrent trip ratio is the feedback resistor, r fb . temperature effects of the mosfet r ds(on) must be reviewed when changing the overcurrent trip level. output voltage monitoring the output voltag e must be tied to the vsen pin to provide feedback used to create a window of operation. if the output voltage is not the reference volt age of 0.8v, it must be scaled externally down to this leve l. the vsen voltage is then compared with two set voltage levels which indicate an overvoltage or undervoltage condition of the output. violating either of these conditions results in the pgood pin output toggling low to indicate a problem with the output voltage. overvoltage the vsen voltage is compared with an internal overvoltage protection (ovp) reference set to 115% of the internal reference. if the vsen voltage exceeds the ovp reference, the comparator simultaneously sets the ov latch and triggers the pwm output low. the drivers turn on the lower mosfets, shunting the converter output to ground. once the output voltage falls below the nominal output voltage, the pwm outputs are placed in three-state. this prevents dumping of the output capacitors back through the lower mosfets. if the overvoltag e conditions persist, the pwm outputs are cycled be tween the two states similar to a hysteretic regulator. the ov latch can only be reset by cycling the vcc supply voltage to initiate a por and begin a soft-start interval. undervoltage the vsen voltage is also compared to a undervoltage (uv) reference which is set to 90% of the internal reference. if the vsen voltage is below the uv reference, the power good monitor triggers pgood to go low. the uv comparator does not influence converter operation. vsen scaling the output voltage, v out , must be fed back to the vsen pin separately from the feedback components to the fb pin. if vsen and fb are tied together, the error amplifier will hold the vsen voltage at the refere nce level while the actual output voltage level could be much different. this would mask the output voltage and pr event the protection features from reacting to undervoltage or overvoltage conditions at the proper time. r isen i fl n -------- -x r ds on () 50 a ------------------------- = (eq. 6) k oc 82.5 a i total ---------------------- - = (eq. 7) r isen i fl n -------- -x r ds on () xk oc 82.5 a ------------------------------------------ - = (eq. 8) r fb v droop xk oc 82.5 a --------------------------------------------- = (eq. 9) ISL6558
11 if the output voltage is not t he same as the internal 0.8v reference, then a resistor divider scaled like the fb resistors is required as shown is figu re 8. otherwise, the output voltage should be tied directly back to the vsen pin without a resistor divider. pgood signal the undervoltage comparator and overvoltage latch feed into the power good monitor and are nor?d together. if either indicates a fault, the power good monitor triggers the pgood output low. a high on this open drain pin indicates proper output voltage. application guidelines layout considerations layout is very important in high frequency switching converter design. with mosfet s switching efficiently at greater than 100khz, the resulting current transitions from one device to another cause voltage spikes across the interconnecting impedances and parasitic circuit elements. these voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device overvoltage stress. careful component layout and printed circuit design minimizes the voltage spikes in the converter. as an example, consider the turnoff transition of the pwm upper mosfet. prior to turnoff, the upper mosfet was carrying the channel current. during turnoff, current stops flowing in the upper mosfet and is picked up by the lower mosfet. any inductance in the switched current path generates a large voltage spike during the switching interval. careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. there are two sets of critical components in a dc-dc converter using a ISL6558 controller and hip660x gate drivers. the switching components are the most critical because they switch large am ounts of energy, and therefore tend to generate equally large amounts of noise. next are the small signal components which connect to sensitive nodes or supply critical bypassing current and signal coupling. a multi-layer printed circuit board is recommended. figure 9 shows the connections of the critical components for one output channel of the converter. note that capacitors c in and c out could each represent numerous physical capacitors. dedicate one solid layer, usually the middle layer of the pc board, for a ground plane and make all critical component ground connections with vias to this layer. dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. keep the metal runs from the ph ase terminal to the output inductor short. the power plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers for the phase nodes. use the remaining printed circuit layers for small signal wiring. the wiring traces from the hi p660x driver to the power mosfet gates and source should be sized to carry at least 1a of current. the switching components and hip660x gate drivers should be placed first. locate the in put capacitors close to the power switches. minimize the length of the connections between the input capacitors, c in , and the power switches. position both the ceramic and bulk input capacitors as close to the upper mosfet drain as possible. locate the output inductors and output capacitors between the mosfets and the load. place the hip660x gate drivers close to their respective channel mosfets. the critical small signal components include the bypass capacitors for vcc on the ISL6558 controller as well as those on vcc and pvcc of the hip660x gate drivers. position the bypass capacitors, c bp , close to the device pins. it is especially impor tant to place the feedback resistors, r fb and r os , and compensation components, r c and c c , associated with the input to the error amplifier close to the fb and comp pins. care should be taken in routing the current sense lines such that the isen resistors are close to their respective pins on the controller. resistor r t , which sets the oscillator fr equency, should be positioned near the fs/en pin. vsen r fb r os v out ISL6558 figure 8. vsen resistor divider configuration fb droop r fb r os ISL6558
12 component selection guidelines output capacitor selection output capacitors are required to filter the output inductor current ripple and supply the load transient current. the filtering requirements are a function of the channel switching frequency and the output ripple current. the load transient requirements are a function of th e slew rate (di/dt) and the magnitude of the transient lo ad current. these requirements are generally met with a mix of capacitors and careful layout. some modern microprocessors can produce transient load rates above 200a/ s. high frequency capacitors are used to supply the initial transient current and slow the rate-of-change seen by the bulk capacitors. bulk filter capacitor values are generally determined by the esr and voltage rating requirements rather than actu al capacitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulne ss of these low inductance components. consult with the manufacturer of the load device for any specific decoupling requirements. specialized low-es r capacitors intended for switching regulator applications are recommended for the bulk capacitors. the bulk capacitor ?s esr determines the output ripple voltage and the initial voltage drop following a high slew- rate transient edge. aluminum electrolytic capacitor esr values are related to case size with lower esr available in larger case sizes. however, the esl of these capacitors increases with case size and ca n reduce the usefulness of the capacitor to high slew-rate transient loading. unfortunately, esl is not a specified parameter. work with your capacitor supplier and measure the ca pacitor?s impedance with frequency to select a suitable component. in most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. output inductor selection the output inductor is selected to meet the voltage ripple requirements and minimize the converter response time to a load transient. in a multi-phase converter topology, the ripple current of one active channel partially cancels with the other active channels to reduce the overall ripple current. the reduction in total output ripple current results in a lower overall output voltage ripple. the inductor selected for the power channels determines the channel ripple current. increasing the value of inductance reduces the total output ripple current and total output voltage ripple. however, increasing the inductance value will slow the converter response time to a load transient. one of the parameters limiting the converter?s response time to a load transient is the time required to slew the inductor current from its initial current level to the transient current level. during this interval, the difference between the two levels must be supplied by the output capacitance. minimizing the response time can minimize the output capacitance required. the channel ripple current is approximated by the following equation: v out +12v via connection to ground plane island on power plane layer island on circuit plane layer l o1 c out c in +5v in phase vcc use individual metal runs comp ISL6558 pwm r t r fb r c c bp fb vsen isen r isen hip6601b c boot c bp c c vcc fs/en pvcc isolate output stages for each channel to help pwm boot r os figure 9. printed circuit board power planes and islands i ch d v in v out ? f sw xl ---------------------------------- x v out v in ----------------- = (eq. 10) ISL6558
13 the total output ripple current can be determined from the curves in figure 10. they provide the total ripple current as a function of duty cycle and number of active channels, normalized to the parameter k norm at zero duty cycle. where l is the channel inductor value. find the intersection of the active channel curve and duty cycle for your particular application. the resulting ripple current multiplier from the y-axis is then multiplied by the normalization factor, k norm , to determine the total output ripple current for the given application. input capacitor selection use a mix of input bypass capacitors to control the voltage overshoot across the mosfets. use ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the rms current. small cerami c capacitors can be placed very close to the upper mosfet to suppress the voltage induced in the parasitic circuit impedances. two important parameters to cons ider when selecting the bulk input capacitor are the voltage rating and the rms current rating. for reliable operation, select a bulk capacitor with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. the rms current requirement for a converter design can be approximated with the aid of figure 11. follow the curve for the number of active channels in the converter design. next determine the duty cycle for the converter and find the intersection of this value and the active channel curve. find the correspon ding y-axis value, which is the current multiplier. multiply the total full load output current, not the channel value, by the current multiplier value found and the result is the rms input current whi c h must be supported by the input capacitors. mosfet selection and considerations the ISL6558 requires two n-channel power mosfets per active channel or more if parallel mosfets are employed. these mosfets should be selected based upon r ds(on) , total gate charge, and thermal management requirements. in high-current pwm applications, the mosfet power dissipation, package selection and heatsink are the dominant design factors. the power dissipation includes two loss components; conduction loss and switching loss. these losses are distributed between the upper and lower mosfets according to duty cycl e of the converter (see the equations below). the conduction losses are the main component of power dissipation for the lower mosfets, q2 and q4 of figure 1. only the upper mosfets, q1 and q3 have significant switching losses, since the lower device turn on and off into near zero voltage. the following equations assume linear voltage-current transitions and do not model power loss due to the reverse- recovery of the lower mosfets body diode. the gate- charge losses are dissipated in the hip660x drivers and don?t heat the mosfets. however, large gate-charge increases the switching time, t sw which increases the upper mosfet switching losses. ensu re that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. a separate heatsink may be necessary depending upon mosfet power, package type, ambient temperature and air flow. k norm v out lxf sw -------------------- - = (eq. 11) 1.0 0.8 0.6 0.4 0.2 0 0 0.1 0.2 0.3 0.4 0.5 duty cycle (v o /v in ) single channel 2 channel 3 channel 4 channel figure 10. ripple current vs duty cycle current multiplier, k cm i total dk norm xk cm = (eq. 12) 0.5 0.4 0.3 0.2 0.1 0 0 0.1 0.2 0.3 0.4 0.5 duty cycle (v o /v in ) current multiplier single channel 3 channel 4 channel 2 channel figure 11. current multiplier vs duty cycle p upper i o 2 r ds on () v out v in ------------------------------------------------------------ i o v in t sw f sw 2 --------------------------------------------------------- - + = (eq. 13) p lower i o 2 r ds on () v in v out ? () v in -------------------------------------------------------------------------------- - = (eq. 14) ISL6558
14 ISL6558 quad flat no-lead plastic package (qfn) micro lead frame plast ic package (mlfp) l20.5x5 20 lead quad flat no-lead plastic package (compliant to jedec mo-220vhhc issue c) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.23 0.28 0.38 5, 8 d 5.00 bsc - d1 4.75 bsc 9 d2 2.95 3.10 3.25 7, 8 e 5.00 bsc - e1 4.75 bsc 9 e2 2.95 3.10 3.25 7, 8 e 0.65 bsc - k0.25 - - - l 0.35 0.60 0.75 8 l1 - - 0.15 10 n202 nd 5 3 ne 5 3 p- -0.609 --129 rev. 3 10/02 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.
15 all intersil u.s. products are manufactured, asse mbled and tested utilizin g iso9000 quality systems. intersil corporation?s quality certifications c an be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com ISL6558 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo se ries symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mo ld flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include inte rlead flash or protrusions. in- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optiona l. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are sh own for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimeter. converted inch dimen- sions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m b s e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m16.15 (jedec ms-012-ac issue c) 16 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.053 0.069 1.35 1.75 - a1 0.004 0.010 0.10 0.25 - b 0.014 0.019 0.35 0.49 9 c 0.007 0.010 0.19 0.25 - d 0.386 0.394 9.80 10.00 3 e 0.150 0.157 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.228 0.244 5.80 6.20 - h 0.010 0.020 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n16 167 0 o 8 o 0 o 8 o - rev. 1 02/02

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